Control Logic CCA A3. - TM-32-5865-216-24-P0024

TM 32-5865-216-24&P

3-5.2 Control Logic CCA A3. Refer to figure 3-3. The control logic

CCA control circuit stores RF switch and stepper motor position data

inputs from decoder CCA A4 into a

and converts the subband and

subband,

25-bit output to feedback CCA S4. In addition, the

and data strobe inputs from decoder CCA A4 are converted into drive

pulse outputs to motor control CCA A2. Table 3-3 lists the control

signals accessed from the control logic CCA test points.

3-5.2.1 RF Switch Decoder Circuit. As shown in figure FO-3, RF

switch decoder circuit U16 through U19, U21B, and U22B converts the

B0 through B4 data into a 32-bit word. The upper seven bits are

applied to the status circuit (U9) and provide the INVALID ADDRESS

output to decoder CCA A4. The lower 25 bits (Band 0 through Band 24)

contain a single low bit that defines the required switch position.

The Band 0 through Band 24 signals are applied to feedback CCA S4.

3-5.2.2 Motor Direction Decoder Circuit. Motor direction decoder

circuit U1 and U8 compares the B0 through B4 input with data stored

in present switch position latch U15. Comparison results determine

the stepper motor M1 rotation direction. The motor direction control

output of U1 passes to two-phase motor command generator U6, U13, and

U20 and to extender CCA AS.

3-5.2.3 Motor Drive Circuit. In the motor drive circuit, each TX\RX

signal specifies the transmit or receive operating mode and is

accompanied by a data strobe signal. NAND gate U10B and OR gate U11A

convert the data strobe input into a COUNTER RESET STB signal that

resets counters U7 and U14. Motor control flip-flop U4B is cleared

by the PWR ON RESET output of multivibrator U2B. The 200-Hz output

of motor drive clock AR1A passes to the CLK input of U4B and the

motor command generator. When clocking starts, the motor command

generator provides drive pulse outputs (Al, A2, B1, B2) to motor

control CCA A2, the Q output of U4B is NANDed by U22A with the TX/RX

signal to provide a low READY output to the status circuit of decoder

CCA A4, and counters U7 and U14 are triggered by the PARALLEL LOAD STB

output of U12C. The low READY signal inhibits receipt of subsequent

TX/RX inputs. If stepper motor Ml is not properly positioned when

counters U7 and U14 are fully incremented, the U7 output sets MTR

DRIVE TIMEOUT low to prevent continuous motor operation. When stepper

motor Ml reaches the proper position, the low bit of the Band 0

through Band 24 output is applied through NAND gate U12B as the SW

FDBK signal. The outputs of flip-flop U4B change states to set the

MTR DRIVE TIMEOUT low, to inhibit the motor command generator, and to

set the READY output high. As READY goes high, the MEM STB output of

U3B triggers strobe generator U2. The Q output of U2A clocks present

switch position latch U15 to store the B0 through B4 data.

3-5.3 Motor Control CCA A2. Refer to figure 3-4. The motor control

CCA converts A1, A2, B1, and B2 drive pulses from control logic CCA

A3 into power outputs to stepper motor M1. The pulses are two-phase,

with Al high when A2 is low and B1 high when B2 is low. Table 3-4

lists the signals accessed from the motor control CCA test points.

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