Figure 1-20. Central Processor Unit Block Diagram.

TM 9-1270-219-13&P

Figure 1-20. Central Processor Unit Block Diagram.

microproccesor to effectively read back the state of the

(a) Temporary data storage is performed by

port.

four 256 x 4 RAMS.

(a). The timer measures time intervals up to

260mS

resolution

32uS

under

microprocessor

(b) The memory control circuitry selects either

control. It is reset by writing into a dedicated memory-

ROM,

RAM

particular

memory-mapped

function

decoding the microprocessor memory control signals and

mapped location and read by performing a read cycle

the five most significant bits from the address bus.

from the same location. The timer can be stopped by

applying a clock interrupt signal from the discrete output

port.

(2) Memory-mapped

Functions.

Information

(3) Serial Inputs and Outputs. T h e m i c r o p r o c e s s o r

transferred to status indicators and output discretes by

h a s a serial input port which is multiplexed with discrete

writing data words to a memory-mapped output port

inputs from BIT monitors, A-D conversion return signal,

w h i c h retains information until updated. Data and control

functions

the

D-A

converter

are

also

output

via

and Data Transmit Request descrete. Any input can be

memory-mapped ports. Each port has the same address as

s e l e c t e d for interrogation by setting up the relevant bit

a particular RAM memory location so data output to the

address on the three least significant bits of the address

p o r t is simultaneously written into the RAM, allowing the

bus.

1-22