Data parity in the previous command is correct.
Tuning operation is correct.
Tunable coupler temperature is within limits.
The frequency band requested is valid.
The antenna is fully deployed.
3-6.1.3 Overtemperature. The parity line state alternates between a
logic high and a logic low at a l-MHz rate when an internal overtem-
perature condition is detected.
The control logic
CCA status circuit consists of RF detector AR1B and invalid address
detector U9. As shown in figure FO-3, detector AR1B receives RF DET
inputs from RF monitor CCA A6 and provides an RF SENSE output to the
control logic CCA A3 logic circuit (U11C) and to decoder CCA A4. The
RF SENSE signal is low (logic O) when the RF monitor CCA detects an RF
Test point TP18 allows verification
input to RF switch assembly S2.
Invalid address decoder U9 receives a
of the RF SENSE signal.
seven-bit input from the control circuit (U16 through U19, U21B, and
U22B). When all the bits are high, the output of U9 indicates the
If any bit is low, the U9-8 out-
requested frequency band is valid.
put indicates the requested frequency band is out of range.
output of U9 passes to the decoder CCA status circuit.
assembly status circuit consists of RF thermostat switch S3, RF
monitor CCA A6, and RFI filters FL1 through FL4. An overtemperature
circuit connects motor temperature thermostat switch S1 and RF
Filters FL1 and FL2 reduce
thermostat switch S3 to decoder CCA A4.
fluctuations in the TEMP DET input from switch S1 and the TEMP DET
output to the decoder CCA, respectively. As shown in figure FO-5,
filters FL3 and FL4 reduce fluctuation in the RF DET outputs from the
RF monitor CCA sensing network to detector AR1B in control logic CCA
POWER DISTRIBUTION CIRCUIT.
Refer to figure 3-6. Power supply CCA Al converts the +28 V dc
input into outputs of filtered +28 and regulated +15, +5, and -5 V dc.
Table 3-5 lists the voltages accessed from the power supply CCA
test points. As shown in figure FO-6, filter L1, L2, C1, C2, C13,
and C14 provides a filtered +28 V dc output to RF relays K1 and K2,
motor control CCA A2, extender CCA A5, and stepper motor Ml. Voltage
regulator AR3 and transistor Q6 convert the filter output into +15 V
outputs to extender CCA A5 and motor control CCA A2. Chopper Q1 and
Q5 and pulse transformer T1 comprise a dc-to-dc converter that
provides +5 V outputs. Comparator AR1 monitors the voltage drop
across resistor R1 and adjusts the chopper Q1 and Q2 duty cycle to
Filter C9 through C11 and C15 passes the +5 V
Diode CR4 and
output to decoder CCA A4 and control logic CCA A3.
filter C6 through C8 pass the -5 V output to decoder CCA A4 and
control logic CCA A3. Voltage divider network R21 and R22 divides
the VREF output of AR3 and provides a precision reference to crowbar
circuit Q2 through Q4 and AR2.