Bandpass Amplifier

Sense oscillator frequency changes resulting from an intrusion will be on the order of 0.1 to 0.4 percent; therefore, the

demodulator output amplitude will be very small and requires a large degree of amplification.

c. Bandpass Amplifier. A schematic diagram of the bandpass amplifier is shown in Figure 6-4. The

bandpass amplifier provides approximately 74 db gain for the signal received from the PLL. By means of the coupling

capacitors C13, C16, and C18, in series with resistors R17, R21, and R25, and the feedback networks made up of R20,

R24, C15, and C17, the bandwidth of the amplifier chain is limited to from .05 to 5 Hz. The noninverting inputs of the

three operational amplifiers are biased by voltage dividers made up of R18, R19, R22, R23, R26, and R27, to minimize

the effects of DC leakage current in the coupling capacitors connected to the inverting inputs. Variable resistor, R29,

changes the voltage gain of the final stage, U5, 2.2 db. This small adjustment is necessary to compensate for

tolerances introduced in the PLL and comparator circuits and is a factory adjustment.

d. Detector and Threshold Circuit. A schematic diagram of the detector and threshold circuit is shown in

Figure 6-5. The output of the bandpass amplifier is connected to the base of Q3A, while the base of Q3B is biased at

about 9.2 VDC by the voltage divider made up of R31 and R32. Because of this bias, there is current flow through and a

drop across R33, holding the emitters of both Q3A and Q3B at about 9.2 VDC. When the input to the base of Q3A from

the bandpass amplifier exceeds the emitter voltage, Q3A conducts causing the drop across R33 to increase, which cuts

off Q3B. Thus, when the voltage on the base of Q3A is greater than the bias on Q3B, the current through R33 is sharply

transferred from Q3B, to Q3A. Since the collector of Q3A is connected to the base of Q1, Q1 is turned on. This

constitutes an upper threshold alarm. CR3 and CR4 are used to prevent reverse base-emitter breakdown of Q3A and

Q3B, due to the large drop across R33. The lower threshold is established similarly by Q2A and Q2B. However, the

output of this pair is taken from the biased transistor, Q2B, causing turn on when the voltage on Q2A is less than the bias

on Q2B. The result is that when the output of the bandpass amplifier is between approximately +9.2 or less than +2.8

VDC, an alarm is generated. This corresponds to a decrease or an increase, respectively, of the capacitance at the

sensor cable input to the CPS.

e. Alarm Generator and Relay Driver. A schematic diagram of the alarm generator and relay driver is shown

in Figure 6-6. During the no-alarm condition, the collector of Q3A (in the detector and threshold circuit) is at ground, or

logic "low" state; conversely, during an alarm state, this point is at +12 VDC or logic "high" state. An alarm duration of

five seconds is required to energize the alarm relay K1; however, because the alarm condition may not last that long, a

one-shot or non-stable multi-vibrator is used to "stretch out" the alarm period to five seconds. This circuit consists of two

NOR gates, U8-A and -B, C19, and R35. R35 maintains a logic high on one input of U8-B, while the other input is

grounded. Thus, the output of U8-B (and one input to U8-A) is normally logic low. Because the oscillator of Q3 is at a

low state (no alarm) both inputs to U8-A are low causing its output to be high. This high is applied to the base of Q3E,

which energizes K1; thus the alarm relay is continuously energized during the no-alarm condition. When an alarm is

generated the collector of Q3 goes high. The duration of this high may be very short (less than the alarm period);

however, the output of U8-A immediately goes low causing two things to happen: (1) Q3E turns off de-energizing K1

(alarm relay), and (2) C19 starts to charge through R35. This causes a momentary logic low at the input of U8-B so that

its output (and input to U8-A) goes to logic high. This condition continues until the capacitor, C19, charges to the

threshold of U8-B (about 7. 5 VDC). This causes the circuit to reset to the initial condition provided that the collector of

Q3E has returned to ground (no-alarm). If it is still high, the relay will remain de-energized (alarm) until it returns to

ground.

f. Tamper Detector. A schematic diagram of the tamper detector is shown in Figure 6-7. When no tamper

alarm is present, both inputs to U8C are low and (as will be discussed later) its output is high. Q2E is turned on, and K1

is continuously energized. An alarm results when either or both inputs to U8C go high, causing Q2E to turn off and K1 to

de-energize. R45, the sense line terminating resistor, forms the bottom leg of a voltage divider with R12, causing

approximately 4.4 VDC to appear at the junction of R12 and R11, which is below the threshold of the NOR gate U8C

which sees this as a logic low. If the sensor cable is cut, R45 is no longer in the circuit, and the voltage at the gate input

rises as C9 charges toward +12 VDC. When this voltage exceeds threshold (about 7.5V) the NOR gate (U8C) output

goes low, generating an alarm. The output of the sense oscillator is taken from the tap on T1, coupled by C5, rectified by

CR2, and applied through R8 to the base of Q3D. Q3D amplifies this signal, which is integrated to a DC level by C7, and

applied to U8C. If the sensor cable is shorted, the sense oscillator is blocked from oscillating by a shot across the

transformer, T1. This results in no signal at the base of Q3D, which is then cut off. A high then appears at the input to

NOR gate U8C, and a tamper alarm is generated by the de-energization of K1.

6-3