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FIGURE 1-10. BIT logic diagram
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TM-9-1270-212-14-P Fire Control Subsystem Helmet Directed XM128 P/N 2277716-00 NSN 1270-00-122-9449 Manual
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Steady-state BIT logic is discussed below cont'd
TM 9-1270-212-14&P
(2) Steady-state BIT logic is discussed below.
different sets of pins instead of sharing common pins. Relay
terminals K1-B1 and -F1 and K2-B1 and -F1 are grounded
(a) Refer to foldout FO-1. When BIT is initiated,
and substitute grounds for the wipers of elevation and
the two outputs for each linkage from amplifier card Al3
azimuth potentiometers R1 through R4 when the relays are
and the one output directly from B4-R2 are connected to
energized. Relay terminal K1-Al is connected to
pins 38, 39, and 40 of comparator card Al1 (foldout
out-of-phase 10 volts ac. representing the pilot k signal, but
FO-8). On Al1, impedance matching and scaling networks
relay terminal K2-A1 is connected to out-of-phase 9.29
AR1, Rl, and R4; AR3, R15, and R18; and AR5, R29, and
volts ac (test signal Gk) from XA15-5. Relay terminal
R32 provide a 200K load and reduce the amplitude of the
K1-C1 is connected to out-of-phase 4.19 volts ac (test signal
input signals to one-ninth of their original value. The signals
Pi) from XAl5-7: K2-C1 is connected to out-of-phase 5.83
are also inverted. Attenuation is required to meet the input
volts ac (test signal Gi) from XAl5-17. Relay terminal
requirements of dual comparators AR2, AR4, and AR6.
K1-El is connected to in-phase 2.01 volts ac (test signal Pj)
The low tolerance level of the dual comparators is
from XAl5-2; relay terminal K2-E1 is connected to
connected to pin 6 of the amplifier, and the upper
in-phase 2.81 volts ac (test signal Gj) from XA15-15. When
tolerance level is connected to pin 3; the input signal is
the relays are energized, these test signals are applied as
divided equally between the low-impedance inputs at pins 4
stated in subparagraph (d) below, with the exception that
the pilot i and j signals (test signals Pi and Pj) are routed
and 7. The out-of-phaae tolerances to the dual-channel
comparators are divided from the out-of-phase 10 volts ac
through azimuth bias circuit card Al4 as for normal
connected to XAl1-12 through dropping resistors R36,
operation of XMl36.
R40, R50, R54, R64, and R68. The in-phase tolerances are
(d) This discussion applies to both EIAs. Then, to
divided from in-phase 10 volts ac connected to XAl1-32
allow the error signals generated within the linkages and
through dropping resistors R8, R12, R22, and R26. If the
Al3-card amplifiers to be measured, relay terminals K3-A1,
signal applied to each comparator is in phase with and
.B1, and -C1 transfer the pilot linkage outputs to XA9-29,
between the upper and lower tolerances, the comparator
.37, and -38 of sequencer card A9 (foldout FO-6), and relay
generates a train of 4-volt, 400-Hz square waves which is
terminals K3-D1, -El, and -F1 transfer the gunner linkage
connected to retriggerable dual one-shots U11 and U12.
outputs to XA9-28, -35, and -39. Deenergized relays A9K1
The period of the string of pulses is shorter than the time
and K2 transfer the pilot linkage outputs to XA11-38,-39,
constant of the one-shots; therefore, the output at pin 10
or 6 remains high. If no signal is applied to each comparator
and -40 (foldout FO-8) by way of XA9-27, -33, and -40.
or if the signal applied is out of the tolerances set, the
Energized relays A9K1 and K2 transfer the gunner linkage
outputs to comparator card Al1 in the same way.
comparator generates a low and the output of the one-shots
remains low.
(e) In both EIAs, the individual buffer amplifiers
(b) Pins XA11-19, -16, and -14 are connected to
are tested when buffer-amplifier relays K1, K2, and K3 are
four-input NAND gate U9 on logic card A10/A15 through
energized. The energized relays connect 5 volts ac and 10
pins XA10/XAl5-40, -38, and -36. If, for example, all three
volts ac to the amplifier inputs and connect the four
signals are high, the signals provide three of the four high
amplifier outputs to test resolver B1 by means of the
inputs required to activate the NAND gate. Enable A is the
connections listed in subparagraph (a). Thus, during the
fourth signal.
BIT, the relays substitute the test resolver for the linkage
resolver and cause one buffer amplifier at a time to be
(c) If a linkage assembly (buffer amplifier,
tested.
linkage, and A13-card amplifiers) produces an improper
output, the BIT logic tests each buffer amplifier in the
(f) Test-resolver B1 inputs (foldout FO-4 or FO-5)
failed linkage assembly by connecting the amplifiers, one at
are connected through the relay to the buffer-amplifier
outputs as explained in (e).  The 28-volt dc excitation for
a time, to test resolver B1 and checking for known
test-resolver outputs. The resolver outputs connected to
the test resolver is connected to B1 -S3 and -S4. Returns are
XA11-24 and -26 are attenuated on card Al1 by
connected to B1 -S7 and -S8 and to -R1 and -R4. The
impedance matching and scaling networks AR7, R43, and
buffer-amplifier outputs are applied to B1 -S1 and -S2, and
R46; and AR9, R57, and R60. The upper and lower
to B1 -S5 and -S6 through resolver external resistors R9 and
tolerances for dual comparators AR8 and AR410 receive
R10, mounted on TB1 between terminals 9 and 10 and 11
power as explained in (a). The lower tolerances are set by
and 12. The B1 -R2 and -R3 outputs are connected to
comparator card Al1 through A11-24 and 26.
dropping resistors R54 and R68 and the upper tolerances,
1-19

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