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Steady-state BIT logic is discussed below
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TM-9-1270-212-14-P Fire Control Subsystem Helmet Directed XM128 P/N 2277716-00 NSN 1270-00-122-9449 Manual
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NOTE - TM-9-1270-212-14-P0057
TM 9-1270-212-14&P
Pullup resistor R25 provides a high at U5-13, applying a
are set by dropping resistors R50 and R64. If the buffer
low at U5-11. The low reset signal at U5-9 insures this state
amplifier connected to test resolver B1 produces a normal
of the tlip-flop. The low at U5-11 is connected to U2-13.
output, dual comparators AR8 and AR10 generate a train
causing U2-12 to go high. The high is inverted at U3-8,
of pulses and dual one-shot U13 produces highs at XA11-8
keeping Q5 cut off and K4 deenergized. Deenergized relays
and XA11-6.
K3 and K4 keep the helicopter pilot linkage (PLT) and
gunner linkage (GNR) fail indicators off. Relay K5 can be
(d) Pins XA11-8 and -6 are connected to
energized by either Q6 or Q7. The power fail enable signal
three-input NAND gate U9 on logic card A10/A15 through
pins XA10/XAl5-35 and -33. If both signals are high, they
at XA10/XAl5-41 is low, (This low is generated by inverter
U2-6 on sequencer card A9 through XA9-23.) The low at
provide two of the three inputs required to activate the
NAND gate. When the BIT function is not active, inputs to,
XA10/XA15-41 is connected to U6-5, where it causes U6-6
four-input and three-input NAND gates U9 are lows.
to be high. This high is connected to U4-12, where it allows
U4-11 to go low. The low reset signal at U4-2 insures this
(e) On logic card A10/A15, when BIT is not
state of the flip-flop. The low at U4-11 is connected to
initiated, pin 9 is open. Twenty-eight volts dc is connected
XA10/XA15-32, where it is called the power fail latch. This
through K2-7 and -5, CR9, K6-2 and -4, and R16 to the
low is connected through XA9-11 to U10-18, where it is a
base of Q8, and through R10 to XA10/XA15-9 and Jl-f.
second enable for decoder U10. On the logic card, the
The high at the base of Q8 causes the transistor to saturate,
U4-11 low is also connected to U4-1, causing U4-3 to go
causing the collector at XA10/XAl5-25 to go low. The low
high. This high is connected to U8-4 and -5. U8-1 and -2 are
at the collector is also connected to NAND gates U1, U4,
held high by pullup resistor R6. With the four inputs high,
U8-6 is low, keeping Q7 cut off and K5 deenergized. The
U5, and U7. Thus, when BIT is not initiated, the reset
enable B signal at XA10/XAl5-34 is low at this time. (This
signal at XA10/XAl5-25 is low.
low is generated by inverter U8-6 on sequencer card A9
through XA9-8.) The low at XA10/XA15-34 is connected
(f) Since the inputs to NAND gates U9 are high
to U6-10, causing U6-8 to go high. This high is connected
only during BIT, the NAND-gate outputs are high. At U9-6,
to U4-9, where it allows U4-8 to go low. The low reset
the high is maintained by pullup resistor R22, and at U9-8,
signal at U4-4 insures this state of the flip-flop. The low at
by pullup resistor R24. The high at U7-10 allows U7-8 to
U4-8 is connected to U1 -5, causing U1-6 to go high. This
be low. The low reset signal at U7-4 insures this state of the
high is inverted at U3-6, keeping Q6 cut off and K5
flip-flop. The low at U7-8 is coupled to U7-5. With two low
deenergized. The go latch not signal at XA10/XA15-26,
inputs, the U7-6 output is high. The low at U7-8 is
connected to U7-3, is high and is connected to U3-4 on
connected to pin 29 and is called skip. The low at U7-8 is
sequencer card A9 through XA9-25. U3-5 is high. The
also connected to U2-9, where it causes U2-8 to be high:
resulting low at U3-6 is connected through XA9-26 and
the high is inverted at U3-10 to a low. This low keeps
XA10/XA15-24 to U2-3, U2-2, and U1-4.
transistor Q3 cut off and K2 is deenergized. Pullup resistor
R23 applies a high to U7-13, allowing U7-11 to go low. The
low reset signal at U7-2 insures this state of the flip-flop.
(i) Power supply card Al2 (foldout FO-9).
This low is connected to U2-10 and to XA10/XAl5-30,
contains test logic that indicates the status of EIA power.
where it is called go latch. The low is connected through
The 18-volt dc output of AR1 is attenuated across divider,
XA9-13 to A9U10-19, where it acts as one enable for
network R1 and R2 and connected as a high to U1-2. The
decoder U10.
12-volt dc output of AR2 is attenuated across divider
network R3 and R4 and connected as a high to U1-4. The
(g) Deenergized relay contacts A10/Al5K2-2 and
28-volt dc input from chassis-mounted PS1 at A12-22 is
-4 apply -6 volts to FET switch Q1, opening the switch.
attenuated across divider network R5 and R6 and
With Q1 open, Q2 is cut off and its collector is high
connected as a high to U1-1. The 10-volt ac input from
(through pullup resistor R1). The high is connected to
chassis-mounted T2 at XAl2-12 and -14 is rectified by
U1-13, where it allows U1-11 to go low. The additional
diodes CR17 and CR18; is attenuated and filtered by R9,
reset-signai low at U1-9 causes U1-8 to be high.
R10, and C16; and is applied as a high to U1-5. The three
U2 inverters connected to XA12-6 form a wired OR gate. If
(h) The high at U9-8 is connected to U5-1,
the output of any inverter goes low, it pulls the other
allowing U5-3 to go low. The low reset signal at U5-5
outputs low also. Thus, if any input to U1 is low, U1-6 is
insures this state of the flip-flop. The low at U5-3 is
high and U2-2 is low. The -6-volt and -18-volt dc outputs
connected to U2-5, causing U2-6 to go high. The high is
are monitored by divider CR19, R7, and CR20, and CR21,
inverted at U3-4, keeping Q4 cut off and K3 deenergized.
R8, and CR22. The voltage at U2-3 and U2-5 is the diode
1-20

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