Quantcast CHAPTER 6 FUNCTIONING OF EQUIPMENT - TM-5-6350-262-14-130016


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TM-5-6350-262-14-13 Sensor Capacitance Proximity DT-548( )/FSS-9 (V) FSN 6350-228-2606 Manual
Figure 6-1. CPS Block Diagram.
6-1. Principal of Operation
The CPS operates by using the capacitance to ground of the protected equipment as one of the frequency-determining
parameters of a sense oscillator. When this capacitance changes, the frequency of the sense oscillator changes. This
frequency shift is detected and processed, and if the shift meets alarm criteria, an alarm is generated.
6-2. Block Diagram Discussion
A block diagram of the CPS is shown in Figure 6-1. The sense line input is routed through a bandpass filter to eliminate
electromagnetic interference outside the bandpass of the filter. The input is then routed through the sensitivity switch to
the sense oscillator. The sense line input terminates at the sense oscillator, and the signal flow from the sense oscillator
to the phase-lock loop (PLL) is the AC generated by the sense oscillator. The PLL acquires the frequency of the sense
oscillator, but when this frequency changes, a correction voltage in the PLL is generated to shift the PLL to the new
frequency, and this correction voltage is routed to the bandpass amplifier. If the correction voltage signal falls within the
bandpass of the bandpass amplifier, it is amplified and routed to a detector and threshold circuit. If the signal meets the
amplitude requirements of the detector and threshold circuit, its output causes the alarm generator and relay driver to
generate an alarm. This is routed to the control unit for visible and/or audible annunciation in accordance with installation
requirements. The sensor cable input is also routed to tamper detection circuitry. Tamper detection results from the
sensor cable being either shorted or open, and depends upon the DC bias parameters of the cable, not on its capacitance
to ground. This DC bias is established by a resistor which terminates the cable at its furthest end. The tamper circuit
contains its own alarm generator and relay driver independent of the capacitance proximity alarm generator and relay
driver. The switch in series with the tamper alarm output generates an alarm if the CPS enclosure is opened. The CPS
power supply consists of an RC filter to eliminate fast-rise voltage spikes on the input, and a voltage regulator to provide
a steady +12 volts from the +20 VDC voltage input which may vary from + 18 to + 22 VDC.
6-3. Circuit Description
All of the circuitry, with the exception of the sensor
cable tamper switch and terminating resistor, is contained on a single circuit card assembly. A schematic diagram of the
circuit card assembly is shown in Figure FO-1. In addition, for clarity, partial schematic diagrams corresponding to the
functional sections of the block diagram are given in this section.
a. Sense Oscillator. A schematic diagram of the sense oscillator is shown in Figure 6-2. This includes the
bandpass filter consisting of C2, L 1, and L2. This is a slow roll off filter having a bandwidth of approximately 10 kHz to
200 kHz. The oscillator is essentially a Hartley type using Q2c (part of an integrated circuit transistor array) as the active
element. The frequency of oscillation is determined by T1, C4, and the external protected capacitance, and is between
approximately 40 kHz and 70 kHz. With a constant external capacitance, the oscillator is stable to within 0.5% over the
required operating temperature range. The two sensitivity ranges, selected by S1, are achieved by a tap on T1. In the
HI sensitivity position, the external capacitance is applied across the entire inductance of T1; in the LO sensitivity
position, the external capacitance is applied across only a portion of the inductance of T1 and therefore has a greater
effect on the frequency of oscillation of the sense oscillator. The low impedance secondary of T1 furnishes an oscillator
output for the phase lock loop.
b. Phase Lock Loop. A schematic diagram of the interconnection of the PLL is shown in Figure 6-3. The PLL
itself is a monolithic integrated circuit and its internal circuitry is now shown; this internal circuitry consists of a stable (0.
5% over the required temperature operating range) voltage-controlled oscillator (VCO), an adaptable filter and
demodulator, a phase comparator, an amplifier, and a low-pass filter.  The free-running frequency of the VCO is
determined by R16 and C10. The capture characteristics and the effective bandwidth of the PLL are determined by C12.
In this application, the PLL is locked on the output of the sense oscillator, which it will follow over any expected deviation
in frequency. Sense oscillator frequency changes cause a corresponding change in the PLL VCO control voltage, which
is designated as the demodulated output and has an amplitude of approximately 300 millivolts peak-to-peak for a 10%
frequency deviation.

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