Analog Inputs

TM 9-1270-219-13&P

(7) A n a l o g I n p u t s . The Analog Channel Select sets a

hold

circuits.

The

resolver

output

peak

voltages

are

c o d e corresponding to one of the analog input channels

defined by:

(fig. 1-25). The input selected is routed to a comparator.

T h e microprocessor outputs an initial guess of the digital

value of the analog voltage; this is converted to an analog

value by the DAC, and presented to the comparator

alongside the input value. The comparator's output is used

indicate

whether

the

guess

was

high

low.

The

Where θ represents a pitch or combined pitch-and-yaw

processor then makes a new approximation, based on the

angle of the probe. Sampled resolver secondary peak

comparator's output. After 12 such approximations the

voltages are fed into the CPU via the A-D converter

digital value is sufficiently close to the analog input.

circuit. The sine and cosine of each relevant angle is

derived

from

the

digital

secondary

peak

voltages

trigonometric

relationships.

(8) A-D and D-A Interface. Figure 1-25 shows how

o n l y one DAC and four analog channel select lines are

able to perform all the A-D/D-A conversions. Note also

(a) An AADS interface test is included to allow

t h a t the analog outputs are fed back through the analog

the CPU to test the operation of the sample and hold

multiplexer to enable further checking of errors. Fixed

circuitry. During this test analog switches connect the

reference voltages are used to perform calibration checks

sample and holds directly to the oscillator, bypassing the

on the DAC within the EPU.

AADS.

(9) O u t p u t P r o t e c t i o n . Each ADS output signal is

(2) A i r T e m p e r a t u r e S e n s o r C i r c u i t . T h e A A D S

short

circuit

protected.

Short

circuits

ground

will

Air Temperature Sensor (ATS) is supplied with constant

t o l e r a t e d indefinitely without damage to the signal output

current from a current source circuit, and the resultant

buffer.

voltage is sensed by a differential amplifier on the analog

interface unit. Voltage ouput from the differential

amplifier is fed to the A-D conversion circuit and the

(a)

Each

output

independently

buffered

digital result is then stored in the CPU memory. The ATS

t h a t potential damage caused by helicopter primary power

constant current source is switched on for a period of

is confined to that signal output only.

30mS once per second while the A-D conversion is

perfomed. This action is controlled by the processor to

reduce effects of self heating.

c. Analog Interface Unit (AIU). The analog Interface

U n i t (AIU) is the analog input and output interface for

(3) Radar Altimeter Input. The radar altimeter

the ADS LRUs. The signals which are processed include

provides a dc analog output (-7mV/ft) to the EPU to

AADS angle resolver signals, Air Temperature Sensor

allow

correction

altitude

outputs

for

ground

effect

(ATS), raw dc analog signals related to PTU pressure

i n d u c e d errors. The input voltage is applied to a buffer

i n p u t s , and outputs to the LAl and to doppler navigation

a n d scaling amplifier, the output of which is fed to the

system. A precision 10 Vdc reference is included on this

A-D conversion circuit. The digital result is stored in the

card. Peak sampling circuitry is used to convert AADS

CPU memory.

resolver

signals

into

voltage

levels

which

can

accepted by the A-D converter.

d. P o w e r S u p p l y U n i t . The helicopter 28 Vdc supply

is filtered in a self contained EMC filter module (fig.

(1) AADS Interface. The oscillator provides a 400Hz

1-27)

and

used

initially

generate

+10

Vdc.

Other

s i n u s o i d a l reference signal to the AADS angle resolvers

voltages,-5 Vdc, -6.2 Vdc and -10 Vdc are generated to

(fig. 1-26). The peak of this reference is detected, and

supply the boost regulator which increases the voltage up

used as a reference against which a peak sampling pulse is

to +80 Vdc by the action of a diode booster type circuit.

generated for the sample and hold circuits. Peak voltages

The 80 Vdc voltage is controlled by networks which sense

of the resolver outputs are sampled by the sample and

1-26