NOTE - TM-9-1270-212-14-P0057

TM 9-1270-212-14&P

pilot and gunner linkages and transfers the linkage outputs

junction drop, or about -0.7 volt. R7 and R8 limit the

to the comparator circuits. The linkages should be in their

current through 5.1-volt zener diodes CR19 and CR32. The

magnetic BIT brackets.

lows at U2-3 and U2-5 are inverted to highs. The 5-volt dc

power is checked on the logic card. Since a 5-volt failure

(c) On sequencer card A9, the high reset signal at

could disable all logic circuitry and prevent a failure

XA9-6 acts as an enabling signal for oscillator U11, clocked

indication, the circuitry attached to A10/Al5Q7 does not

flip-flop U9, and four-bit counter U4. At U3-13, the high

require 5 volts for operation. A10/Al5U8 receives its

excitation from a divider consisting of 5.1-volt zener diode

has no immediate effect except to enable a change of state

CR6 and R8, which is connected to 28-volt dc input power.

when the high on U3-9 changes.

If the 5-volt power fails, U8-1 and -2 go to ground through

R7, and the low inputs provide a high at U8-6; this turns on

(d) The high on A9U11-4 causes this oscillator to

Q7 and energizes K5. The 28 volts dc connected to K5-3 is

generate 5-ms-wide pulses at 100-ms intervals at U11-3; this

connected through XA10/XAl5-23 and J1-w to the EIA

is a pulse rate of 10 Hz (foldout FO-2). The 10-Hz signal is

fail indicator in the helicopter.

connected to U9-2 and to U5-1. U9 is a clocked flip-flop

that is triggered on the trailing edge (down slope) of each

NOTE

oscillator pulse. The result is a 5-Hz square wave (clock) at

U9-6 (foldout FO-2). At U5-1, the 10-Hz pulses act as

The EIA fail indicator in the AH-lS(Mod)

momentary enables to the NAND gate.

helicopter is labeled INTFC; in the AH-1S heli-

, this indicator is labeled

(e) The square-wave output at A9U9-6 is

copter

EIA.

connected to the clock input at U4-2 and to NAND gate

U5-2. At the NAND gate, coincidence only occurs between

the oscillator pulses at U5-1 and the clock pulses at U5-2

(j) The reset signal at XA10/XAl5-25 is

before the down slope of the clock pulses. The

connected through XA9-6 to U11, U9, and U4 of sequencer

negative-going pulses at U5-3 are inverted at U8-2 and

card A9 and also to flip-flop U3. At U11, U9, and U4, the

appear as a positive-going train of 5-ms strobe pulses

low inhibits operation, respectively, of the oscillator, the

(foldout FO-2). The strobe pulses are connected to U5-12

clocked flip-flop, and the four-bit binary counter. At U3,

and U5-10.

the low sets the flip-flop; this cuts off transistor Q5, causing

its output to go high through relay coils K1 and K2 and

(f) A9U4 is a four-bit binary counter with a

X49-18 to 28 volts.

master reset at pin l; a preset at pins 3, 4, 5, and 6; a preset

enable at pin 9; and outputs at pins 11 through 14. The

(3) BIT operation is discussed in the following

counter can be stopped, started, reset, and preset. The four

paragraphs.

outputs, each with two states (high and low), provide 16

different outputs (24). In this application, the presets are

(a) Power to initiate BIT comes from the BIT

used to jump the output count to a binary 6 if certain logic

switch in the helicopter to J1-f of the EIA and to XAl0-9.

conditions are met. The 5-Hz square-wave input at U4-2

When the BIT switch is actuated, 28-volt dc aircraft power

causes the counter to provide binary outputs on pins 11

is connected through XAl0XAl5-9 and R10 to the base of

through 14. These outputs are connected to 1-in-16

Q8 and through CR7 to K6. K6 energizes and the 28 volts

decoder U10 and drive the decoder to produce

dc on K6-2 is transferred to K6-3, latching the relay in the

negative-going, 200-ms-wide sequential pulses at pins U10-1

energized condition. When the BIT switch is released, the

through U10-13 (foldout FO-2). The inputs at U10-18 and

28 volts dc is removed from the base of Q8, and R11 pulls

-19 must remain low for the decoder to operate. If either

the base to near ground potential; this cuts off Q8, causing

input goes high, the decoder stops decoding.

the reset signal to go high. On card A10/Al5, this high

becomes one enabling signal to NAND gates U1, U4, U5,

and U7. Refer to foldout FO-2 and note that, as the BIT

(g) As indicated in b, the first test checks power.

switch is released, the reset signal at XA10/XA15-25 goes

At time zero, when the reset pulse goes high (foldout

high.

FO-2), A9U10-1 (foldout FO-6) is already low. The low,

inverted to a high, is connected through XA9-23 and

(b) When K6 energizes, relay contacts K6-7 and -6

XA10/XAl5-41 (foldout FO-7/FO-10.1) to provide one

apply 28 volts dc through XAl0/XAl5-10 to energize

high at U6-5. If EIA power is normal, XA10/XA15-31 will

chassis relays K1, K2, and K3. Refer to foldout FO-1 and

be high; this high is inverted at U6-3 to provide a low at

observe that this action applies fixed inputs to both the

U6-4. The output at U6-6 remains high and U4-11 remains

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