reference signals that simulate turret or amplifier inputs are
the amber INTFC (or EIA), PLT, or GNR indicator lights.
connected within the EIA (foldout FO-4 or FO-5).
If the test is to be repeated for verification of the failure,
momentarily reactuate the HSS BIT switch. If the failure
(a) All eight buffer amplifiers have common
is to be cleared to enable partial operation of the system,
connections as follows: pin 17 in-phase 5 volts ac (test
momentarily interrupt EIA power by setting the helicopter
signal C on foldout FO-4 and test signal TR on foldout
MASTER ARM switch to OFF and then back to STBY.
FO-5); pin 22 in-phase 10 volts ac; pin 18 B1-S2 (test
b. Basic Operation.
resolver); pin 14 B1-S6; pin 25 B1-S1; and pin 21
B1-S5. The in-phase 5-volt ac signal originates at
(1) To accomplish a BIT, the EIA contains a network
XA10/XA15-3 from a divider network on the A10/A15
of relays and digital and analog logic that, when triggered,
card. The in-phase 10-volt ac signal originates at T2-1,
tests EIA power, buffer amplifiers, linkages, and the signal
output amplifiers as a system. If the test parameters are
met, the green GO indicator is lighted. If a power failure is
detected, the test sequence stops immediately and lights the
The discussion in (b) below applies to the EIA
EIA fail (INTFC or EIA) indicator. If a linkage failure is
used in XMl28 (foldout FO-4) and the
detected, the logic systematically tests the related buffer
discussion in (c) below applies to the EIA used
amplifiers, one at a time, and then lights the appropriate
in XM136 (foldout FO-5). A comparison of
fail indicator (INTFC or EIA, PLT, or GNR).
these two foldouts will show that the basic
difference in the test circuits for the two EIAs
(2) Figure 1-10 illustrates the BIT logic sequence.
is that there are three more test circuits in the
The time delay from BIT initiate through the logic
EIA used in XM136; these circuits can be
sequence shown on the left side of the figure is about 0.3
traced from J1-t, -u, and -v. These circuits are
second. A worst-se failure logic sequence is completed in
r e q u i r e d b e c a u s e of the azimuth bias
compensation applied by card A14 to the
signals for the pilot linkage in XM136; this
(3) The BIT circuitry is located entirely within the
compensation makes it impossible to use the
EIA and consists of the following: relays K1, K2, K3 in
same circuits for both the pilot linkage and the
each of the eight buffer amplifiers (see fig. 1-12) and, in the
gunner linkage. In the EIA used in XMl28, the
EIA chassis, relays K1, K2, and K3 (foldout FO-4 or FO-5),
linkages use the same test circuits.
test resolver B1, sequencer printed circuit (PC) card A9
(foldout FO-6), logic card A10/A15 (foldout
(b) This discussion applies only to the EIA used in
FO-7/FO-l0.1), and comparator card Al1 (foldout FO-8).
XM 128. Relay terminals Kl-Al and K2-A1 are connected
The logic is arranged to check power first, then the pilot
to out-of-phase 10 volts ac from T2-4, and relay terminals
linkage, and lastly, the gunner linkage. After the power
K1-Bl and -F1 and K2-B1 and -F1 are grounded. Relay
check, the BIT operates by connecting, with the relays,
terminals K1-Cl and K2-C1 are connected to out-of-phase 5
known voltage inputs to the linkages and checking for
volts ac from XA10-7. Relay terminals K1-El and K2-E1
known outputs from the amplifiers on amplifier card A13.
are connected to in-phase 2.5 volts ac from XAl0-2. When
If the pilot linkage fails, the logic tests buffer amplifiers Al,
relays K1, K2, and K3 are energized during the BIT test,
A3, A5, and A7 one at a time, stores the results, and then
relay terminals Al, Cl, and El of relays K1 and K2 provide
tests the gunner linkage. If the gunner linkage fails, the
the following test signals: the k signal is out-of-phase 10
logic tests buffer amplifiers A2, A4, A6, and A8 one at a
volts; the i signal is out-f-phase 5 volts; and the j signal is
time and stores the results. The results are displayed. An
in-phase 2.5 volts. At the same time, relay terminals B1 and
EIA failure takes precedence over a pilot or gunner linkage
F1 of relays K1 and K2 substitute grounds for the wipers of
failure; however, the BIT circuitry is capable of indicating a
elevation and azimuth potentiometers R1 through R4.
failure in both pilot and gunner linkages if, for example,
both linkages were left in the stow position at the time BIT
(c) This discussion applies only to the EIA used in
XM136. When relays KI, K2, and K3 are energized for the
c. Detailed Circuit Analysis.
BIT test, relay K1 transfers the pilot test signals and relay
K2, the gunner test signals. The test-signal outputs from
logic card Al5 (see foldout FO-10.1) differ in value
(1) Hardwired BIT signals are discussed below. Refer
between the gunner linkage and the pilot linkage and use
to foldout FO-1. To enable a BIT, a number of hardwired