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Power supply control unit
TM-9-1240-369-34 Range Finder Fire Control: (Laser) AN/VVG-1 (1240-00-470-2156) Manual
Interface circuit card
C 1, TM 9-1240-369-34
signal itself (or the simulated video signal if the laser is in
for this purpose. The range-counter generates one step
the test model).  If the video gate is enabled, video
count each time the RANGE switch is pressed.  and
pulses are passed to the start-stop and binary flip-flop
resets itself after the fourth range signal.  The video
circuit.  This circuit includes three high-speed binary
inhibit circuit contains coincidence circuits to monitor the
counters, each controlled by a start-stop flip-flop. The
range counter output. and generates a signal to inhibit
counting sequence is started by the leading edge of the
the maximum range circuits when the number of replies
leakage video pulse that corresponds to A-trigger
processed agrees with the number of times the RANGE
development, not by the A-trigger signal, which simply
switch has been pressed. The test oscillator is not used
sets the start-stop flip-flops to a state of readiness to
in the test mode normally; it is turned on when the power
begin  the  counting.
This  introduces  the  delay
supply unit cover is removed, thus closing a pressure-
encountered in the video amplifier and gating system into
sensitive interlock switch. The oscillator then generates
the counters. in order to avoid having to compensate for
a pulse train at 1000 prf so that an oscilloscope can be
that delay so that fictitiously long ranges will not be read
used for troubleshooting.
(d) Reply gating card (operational circuits).
out.  The three counters count high-frequency pulses
generated by a crystal controlled oscillator.  and fed
The operational circuitry of the reply gating card includes
continuously to the clock pulse inputs of the binary flip-
an oscillator, counters, logic and gating circuits. Initial
flops. The outputs of the binary flip-flops are buffered
resetting of all circuits connected to the reset signal bus
and applied to the counter card.
is accomplished by a delay circuit, the turn-on reset OR
(e) Select logic card. The select logic circuit
gate (shared with simulated reset signal and an inverter.
card assembly contains logic for counter selection. The
The 10 km monostable multivibrator generates a turn-off
reply select logic circuit produces outputs representing
signal for the maximum range gate. At the end of a time
various combinations of the reply count.  which are
period corresponding to the full capacity of the counters,
applied to the select control logic circuit. First, second.
it resets the maximum range flip-flop to the inhibit state,
or last signals are applied from the RANGE RETURN
preventing  any  further  video  replies  from  being
SELECTOR pushbuttons on the commander's control
processed.  It also provides an enabling signal to the
unit to the select control logic circuit, and compared to
select enable logic. The maximum range flip-flop and
the other inputs to generate a select 1, select 2, or select
gate circuit is in the normal inhibited state at the start of
3 signal. thus determining which return will be displayed
any ranging sequence.  It is enabled by the A-trigger
signal gated by the output of the reset and malfunction 7
on the RANGE (METERS) indicator.
(f) Counters card. The counters circuit card
logic, which is on briefly when the reset signal occurs
due to flashtube triggering.  Subsequently, it may be
assembly contains the circuitry that counts the clock
inhibited either by the 10 km gate, or by the 9995 signal
pulses during the interval between transmission of the
(the "counter full' signal developed in the counters circuit
laser pulse and detection of the reflected replies. The
card assembly), or by an inhibit signal applied by the
card contains three identical decade counter circuits with
replies counter when the eight reply has been received.
buffer gates. The three inputs, counter 1, counter 2, and
The minimum range flip-flop and gate circuit is enabled
counter 3 are applied to the correspondingly numbered
by the reset pulse gating of the A-trigger signal.
counter, causing the counter to count as long as input
However, it is immediately set to the inhibit state by the
pulses are applied. The signals on the three input lines
video pulse that is generated by leakage of light back
are terminated in sequence, under control of the counter
into the receiver from the transmitter at the time of
gating logic. The outputs of each counter are applied in
transmission, and it remains in the inhibited state long
BCD form to the commander's control unit for display on
enough to prevent video generated from backscattered
the RANGE (METERS) indicator. Counter 3 contains a
light from entering the counter start-stop flip-flops. At the
DTL integrated circuit that processes the outputs for the
end of the minimum-range period, the minimum range
fourth (units) readout indicator which indicates the
signal from the counters card changes the state back to
minimum 5-meter increment and therefore needs only
The enabling minimum range gate and
two-state capability (0 and 5). Counter 3 also provides
maximum range gate signals are applied to the video
information for the minimum and overrange logic
gate, a four-input NAND gate. One of the inputs is used
circuitry, which generates three outputs used to inhibit
only during test to simulate a fourth reply by briefly
circuits in the reply gating and select logic cards. These
interrupting the third video. The fourth input is the video
outputs are the overrange signal, developed when the

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