Figure 2-2. Detector location - test setup.
After each group of four simulated forced penetration attempts prior to a second attempt
Or four simulated forged penetrations) the timing circuit mud be reset by jumpering the
INT test point to signal ground (terminal 8 of TB1`
(3) If a simulated forced penetration is detected, identify the detector location and record the processsor
SENSITIVITY control setting for that location and proceed to the next detector location and repeat the above procedure
until all locations have been tested.
(4) If a simulated forced penetration is not detected, advance the processor SENSITIVITY control to the next
higher setting (that is, from 1 to 2, 2 to 3, 3 to 4, etc.) and repeat steps (2) and (3) above for each higher control setting.
(5) Preliminary adjustments are complete after location testing of all detectors and recording respective
processor SENSITIVITY control settings for each location. The highest processor SENSITIVITY control setting recorded
during the preliminary adjustments will be the final setting after the permanent installation and interconnections.
(6) Disconnect the test setup and retain the fabricated cables for possible reuse during bench troubleshooting
d. Processor/Detector Vibration Signal Test. Following the individual test of each detector location (temporarily
interconnected) must be per. formed. This test evaluates the operation with all detectors connected and verifies the
GAIN levels of