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Figure 6-2. Typical multivibrator/integrator relationship - TM-5-6350-262-14-20029
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TM-5-6350-262-14-2 Processor Passive Signal Ultrasonic MX-9443( )/FSS-9(V) FSN 6350-228-2548 Receiver Passive Signal Ultrasonic Manual
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CHAPTER 7 DIRECT SUPPORT (INTERMEDIATE) MAINTENANCE INSTRUCTIONS - TM-5-6350-262-14-20031
processor/receiver ultrasonic passive signal operat-
frequency as the SYNC pulse frequency, the output
ing band (20 kHz to 30 kHz). Without the synchroniz-
at the drain terminal is a dc level and is completely
ing pulse from the processor/transceiver ultrasonic
rejected by high pass filter components C17-R26 and
motion signal and the band rejection filter in the
C21-R3. For all other frequencies received, the
processor a continuous alarm would be generated.
output will be the difference frequency. This techni-
The processor/transceiver ultrasonic motion signal
que permits complete attenuation of the
provides a synchronizing pulse for use when both
processor/transceiver ultrasonic motion signal au-
equipments are operating in the same environment.
tomatically without the need for adjustment. The
The SYNC pulse input to the processor is a 26.3 kHz
adjacent signal attentuation is negligible. In effect, it
triangular waveform with a peak to peak voltage of
is an automatic tracking notch rejection filter.
2.3 volts. This waveform is regenerated by sync pulse
Unwanted high frequency components are rejected
regenerator Q4 which has a square wave output
by an active low pass filter consisting of Q6 and Q7
pulse of approximately 5 microseconds at 10.5 volts
which in turn drives amplifier Q8 and Q9. The
remainder of the functional description is the same
and a period of 38 microseconds. With the appro-
as described above.
priate connections performed at TB 3 for incorporation of
the band rejection filter between broadband amplifier Q3
6-4. DC Voltage Regulation
and amplifier Q8 and Q9, the circuit operates as a notch
rejection filter.
Power for operating the processor and the receiv-
Mixer Q5 is gated at the precise frequency of the
ers is provided by the J-SIIDS control unit; +20 2
processor/transceiver ultrasonic motion signal.
Vdc, regulated. A block diagram of the power
Sounds
regulator is shown in figure FO-2, (located at rear of
received
(generated by
the
processor/transceiver ultrasonic motion signal) and
manual). Diode CR5 in the positive line of the input
amplified by broad-band amplifiers Q1, Q2, and Q3,
+20 Vdc is so oriented as to offer circuit protection
are applied to the source (S) terminal of mixer Q5.
against accidently reversing the input power polar-
The mixer output at the drain (D) terminal is the
ity connection to the processor. Voltage regulator Z1
difference frequency (in the audio range) between
regulates the input dc power at an output of + 12 Vdc
that at the gate and that at the source. When a
which is used throughout the processor/receiver
received signal, by the receiver, is at the precise
ultrasonic passive signal.
6-4

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